Integrated circuits are manufactured on silicon wafers. A silicon wafer comprises a large number of integrated circuits, typically thousands. The testers used for testing integrated circuits comprise a limited number of input/output connections with the silicon wafer, which cannot be increased.
In order to test all the integrated circuits on a silicon wafer, the tester comes into contact, by means of a probe card, with rectangular regions of the integrated circuit several times in order to establish an electrical connection with the integrated circuit. Several integrated circuits are tested simultaneously in order to reduce the time taken for testing the silicon wafer.
The larger the number of integrated circuits tested in parallel, the shorter the time needed for testing the silicon wafer. The larger the number of test probes used for testing an integrated circuit, the smaller the number of integrated circuits tested in parallel because of the limitation imposed by the number of input/output connections and test probes of the tester.
In addition, integrated circuits on silicon wafers have an internal clock, the frequency of which varies significantly from one integrated circuit to another. The result is a not insignificant difficulty in testing integrated circuits.
The aim of the present invention is to solve the drawbacks of the prior art by proposing a test method and device in which only one input/output connection is necessary for testing an integrated circuit with an internal clock frequency that is not known to the tester.